1. Field of the Invention
The present invention relates generally to a semiconductor dev ice and a method for manufacturing the same. More specifically, the i nvention relates to a stacked semiconductor memory device using a ferr oelectric or a high-dielectric (high-xcex5 material (xcex5: permittivity)) film for a capacitor of a memory cell, and a method for manufacturing t he same.
2. Description of the Prior Art
FIG. 9 is a sectional view of a structure of a memory cell of a conventional stacked semiconductor memory device using a ferroelectric or high-dielectric film for a capacitor.
In the surface part of a silicon substrate 1, an element isolating film 2 for isolating element regions is formed every one memory cell, and three gate diffusion layers 4 are formed at regular intervals every one memory cell. On each of portions serving as channel regions between adjacent two of the gate diffusion layers 4 of the silicon substrate 1, a gate 3 of each of MOS transistors is formed so that the end portion of the gate 3 overlaps with the gate diffusion layers 4 arranged on both sides. A first interlayer insulator film 5 is formed on the silicon substrate 1, on which the gates 3 have been formed. A first contact holes 6xe2x80x2 is formed in the first interlayer insulator film 5 above each of the gate diffusion layers 4. In each of the first contact holes 6xe2x80x2, a first contact interconnection layer 6 is formed.
For each memory cell, a second interconnection layer 8 is connected to one of the three gate diffusion layers 4, which is commonly used for two of the MOS transistors, via one of the first contact interconnection layers 6, and a first interconnection layer 7 is connected to each of two of the gate diffusion layers 4, each of which is dedicated for a corresponding one of two of the MOS transistors, via one of the first contact interconnection layers 6. A second interlayer insulator film 9 is formed on the first interlayer insulator film 5, on which the first interconnection layer 7 and the second interconnection layer 8 have been formed. On the second interlayer insulator film 9, there are formed capacitors, each of which has a capacitor bottom electrode 10, a capacitor insulator film 11 and a capacitor top electrode 12, so that each of the capacitors corresponds to each of two of the three gate diffusion layers 4, each of which is dedicated for a corresponding one of two of the MOS transistors.
A third interlayer insulator film 13 is formed on the second interlayer insulator film 9, on which the capacitors have been formed. In order to connect the third interconnection layer 7 to the capacitor top electrode 12, a second contact hole 14xe2x80x2 is formed in portion of the second interlayer insulator film 9 and the third interlayer insulator film 13 above each of the first interconnection layers 7, and a third contact hole 15 is formed in a portion of the third interlayer insulator film 13 above each of the capacitors. A second contact interconnection layer 14 is formed in each of the second contact holes 14xe2x80x2, and a third contact interconnection layer 15 is formed in the third contact hole 15xe2x80x2. A third interconnection layer 16 of a multilayer interconnection layer is formed on the third interlayer insulator film 13 for connecting the first interconnection layer 7 to the capacitor top electrode 12 via the second contact interconnection layer 14 and the third contact interconnection layer 15. Moreover, an interconnection protecting insulator film 17 is formed on the whole surface of the third interlayer insulator film 13, on which the third interconnection layer 16 has been formed.
The above-described stacked semiconductor memory device functions as a non-volatile memory, such as an EPROM and an EEPROM, when the capacitor insulator film 11 between the capacitor bottom electrode 10 and the capacitor top electrode 12 is formed of a ferromagnetic having a spontaneous dielectric polarization while no electric field is applied, and functions as a volatile memory, such as a DRAM, when the capacitor insulator film 11 is formed of a high-dielectric having a high dielectric.
FIGS. 10 through 12 are sectional views showing a process for manufacturing the memory cell of the conventional stacked semiconductor memory device shown in FIG. 9.
The memory cell of the conventional stacked semiconductor memory device of FIG. 9 is produced by a following manufacturing method.
First, as shown in FIG. 10, an element isolating film 2 for isolating regions is formed every one memory cell in the surface part of a silicon substrate 1 by a thermal oxidation and a photolithography so as to have a thickness of, e.g., about 5000 angstroms(1 angstrom=10 nm). Thereafter, for each one memory cell, a gate oxide film 3a of a gate 3 of a MOS transistor is formed on the silicon substrate 1 by the thermal oxidation so as to have a thickness of, e.g., about 100 angstroms. In addition, a tungsten silicide layer serving as a gate interconnection layer 3b of the gate 3 is deposited on the gate oxide film 3a by a CVD method so as to have a thickness of, e.g., about 2000 angstroms. Moreover, a silicon nitride film serving as a gate protecting film 3c of the gate 3 is deposited on the gate interconnection layer 3b by the CVD method so as to have a thickness of, e.g., about 1000 angstroms. After the gate oxide film 3a, the gate interconnection layer 3b and the gate protecting layer 3c are formed, two gates 3 of MOS transistors are formed every one memory cell by the photolithography and an anisotropic etching (e.g., RIE). After the gates 3 are formed, three gate diffusion layers 4 serving as sources and drains of the MOS transistors are formed every one memory cell by an ion implantation and a thermal diffusion.
Then, as shown in FIG. 11, a first interlayer insulator film 5 is deposited by the CVD method so as to have a thickness of, e.g., about 6000 angstroms. In a portion of the first interlayer insulator film 5 above each of the gate diffusion layers 4, i.e., in a portion for allowing a first contact interconnection layer 6 to be formed, a first contact hole 6xe2x80x2 is formed by the photolithography and the RIE. After the first contact hole 6xe2x80x2, a tungsten layer having a thickness of, e.g., about 4000 angstroms, is deposited by the CVD method so as to be embedded in the first contact hole 6xe2x80x2, and etched to the surface of the first contact hole 6xe2x80x2 by a isotropic etching (e.g., CDE) to form the first contact interconnection layer 6. After the first contact interconnection layer 6 is formed, a tungsten layer is deposited by the CVD method so as to have a thickness of, e.g., about 4000. Then, for each memory cell, a second interconnection layer 8, which is connected to the first contact interconnection layer 6 on one of three gate diffusion layers 4 commonly used for two of the MOS transistors, and a first interconnection layer 7, which is connected to the first contact interconnection layer 6 on each of two of the gate diffusion layers 4 dedicated for two of the MOS transistors, respectively, are formed by the photolithography and the RIE.
After the first interconnection layer 7 and the second interconnection layer 8 are formed, a second interlayer insulator film 9 is deposited by the CVD method so as to have a thickness of, e.g., about 3000 angstroms, on the first interlayer insulator film 5, on which the first interconnection layer 7 and the second interconnection layer 8 have been formed, as shown in FIG. 9. After the second interlayer insulator film 9 is deposited, a platinum (Pt) film serving as a capacitor bottom electrode 10 of a capacitor is deposited by a sputtering method so as to have a thickness of, e.g., about 2000 angstroms, and a PZT (lead (Pb) zirconate titanate) film serving as a capacitor insulator film 11 of the capacitor is deposited thereon by the sputtering method so as to have a thickness of, e.g., about 3000 angstroms. Moreover, a platinum film serving as a capacitor top electrode 12 of the capacitor is deposited thereon by the sputtering method so as to have a thickness of, e.g., about 2000 angstroms. After the platinum film, the PZT film and the platinum film are sequentially formed, the capacitor top electrode 12 is formed by the photolithography and the RIE. Thereafter, the capacitor insulator film 11 and the capacitor bottom electrode 10 are formed by the photolithography and the RIE.
After the capacitor having the capacitor top electrode 12, the capacitor insulator film 11 and the capacitor bottom electrode 10 is formed, a third interlayer insulator film 13 is deposited on the second interlayer insulator film 9, on which the capacitor has been formed, by the CVD method so as to have a thickness of, e.g., about 6000 angstroms, as shown in FIG. 9. After the third interlayer insulator film 13 is deposited, a second contact hole 14xe2x80x2 is formed in a portion of the third interlayer insulator film 13 above the first interconnection layer 7 by the photolithography and the RIE. Moreover, a third contact hole 15xe2x80x2 is formed in a portion of the third interlayer insulator film 13 above the capacitor top electrode 12 by the photolithography and the RIE. After the second contact hole 14xe2x80x2 and the third contact hole 15xe2x80x2 are formed, an aluminum layer having a thickness of, e.g., about 40 angstroms, is deposited by the sputtering method so as to be embedded in the second contact hole 14xe2x80x2 and the third contact hole 15xe2x80x2. After the aluminum layer is deposited, the deposited aluminum layer is processed by the photolithography and the RIE so as to form a second contact interconnection layer 14 in the second contact hole 14xe2x80x2, a third contact interconnection layer 15 in the third contact hole 15xe2x80x2, and a third interconnection layer 16 of a multilayer interconnection layer on the third interlayer insulator film 13. Thereafter, an interconnection protecting insulator film 17 is deposited on the third interlayer insulator film 13, on which the third interconnection layer 16 has been formed, by the CVD so as to have a thickness of, e.g., about 6000 angstroms. Thus, the conventional memory cell of the stacked semiconductor memory device shown in FIG. 9 is completed.
However, in the above-described conventional memory cell of the stacked semiconductor memory device using the ferroelectric or high-dielectric film for the capacitor and in the method for manufacturing the same, there is the following problem. That is, there may be a problem in that the adverse influence of the etching remarkably deteriorates characteristics of the capacitor. More specifically, the adverse influence of the etching, particularly the RIE, for forming the third contact hole 15xe2x80x2 for establishing the contact connection to the capacitor top electrode 12 using the metal interconnection (the third contact interconnection layer 15) after forming the capacitor, and the adverse influence of the reduced atmosphere in the process for forming the multilayer interconnection layer (the third interconnection layer 16) after forming the capacitor, remarkably deteriorate characteristics, such as charge holding characteristic and reliability, of the capacitor.
On the other hand, if the etching for forming the third contact hole 15xe2x80x2 is carried out by the CDE in order to establish the contact connection to the capacitor top electrode using the metal interconnection layer, the adverse influence on the capacitor is decreased. However, since the contact opening portion is wide, if the capacitor top electrode 12 is small, etching proceeds to the vicinity of the capacitor insulator film 11, so that it is difficult to form the third contact hole 15xe2x80x2. Therefore, when the third contact hole 15xe2x80x2 is formed by the isotropic etching, the capacitor top electrode 12 must be sufficiently large, so that the scale down for high density integration is prevented.
It is therefore an object of the present invention to provide a semiconductor device of capable of preventing the deterioration of characteristics, such as charge holding characteristic and reliability, of a capacitor of a memory cell of a stacked semiconductor memory device using a ferroelectric or high-dielectric film for the capacitor, without preventing the scale down for high density integration.
It is another object of the present invention to provide a method for manufacturing such a semiconductor device.
According to one aspect of the present invention, there is provided a semiconductor device comprising a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate; a capacitor formed on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode; a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which has the same level as that of a surface of said capacitor top electrode.
According to the above-described semiconductor device, the surface of the capacitor top electrode, such as the top electrode of a stacked high-dielectric capacitor, may be exposed at the same time that the interlayer insulator film formed on the top electrode is flattened. Thus, it is possible to easily establish the electrical connection to the electrode of the capacitor. In addition, since no interlayer insulator film exists in the connection part on the electrode of the capacitor, it is possible to decrease the thickness of the stacked capacitor, which tends to increase the thickness of the device, and it is possible to decrease the difference in level caused by processing. In addition, the surface of the top electrode of the stacked high-dielectric capacitor may be used as a stopper to flatten the interlayer insulator film on the capacitor top electrode. Thus, it is possible to easily detect the processing end particularly when a chemical mechanical polishing (CMP) is used, and it is possible to form an interconnection connection layer on the whole of the capacitor top electrode. Therefore, the processing margin for forming a contact interconnection layer to the capacitor top electrode by the photolithography can be larger than that for forming only by a contact hole and a contact interconnection layer, and the process can also be simplified. Moreover, since the surface of the capacitor top electrode exposed by the flattening of the interlayer insulator film on the capacitor top electrode has substantially the same level as that of the surface of the interlayer insulator film, it is possible to improve the processing margin in the photolithography while improving the controllability of processing particularly in a step of forming a multilayer above the capacitor top electrode.
According to the present invention, since the surface of the top electrode of the stacked high-dielectric capacitor may be exposed at the same time that the interlayer insulator film formed on the top electrode is flattened, it is possible to easily establish the electrical connection to the electrode of the capacitor. In particular, it is possible to reduce the deterioration of characteristics of a ferroelectric capacitor which tends to be under the adverse influence of the anisotropic etching. In addition, since the surface of the top electrode of the stacked high-dielectric capacitor may be used as a stopper to flatten the interlayer insulator film on the capacitor top electrode, it is possible to easily detect a processing end, and it is possible to decrease the thickness of the capacitor top electrode and the total thickness of the interlayer insulator films on the capacitor top electrode.
In addition, according to the present invention, since the interlayer insulator film below the capacitor bottom electrode of the stacked ferroelectric capacitor may be flattened and since the surface of the capacitor top electrode may be used as a stopper to flatten the interlayer insulator film on the capacitor top electrode, the surface of the capacitor top electrode exposed by the flattening of the interlayer insulator film on the capacitor top electrode has substantially the same level as that of the surface of the interlayer insulator film. Therefore, in a step of forming a multilayer above the capacitor top electrode, it is possible to improve the processing margin in the photolithography while improving the controllability of processing, and it is possible to easily process layers formed above and below the capacitor electrodes, so that it is possible to reduce the adverse influence on the ferroelectric capacitor insulator film due to excessive etching in the multilayering step including the capacitor electrode forming step.